“Reliable Hardware Infrastructure for Upcoming AI Chips”

February 10-12, 2025, IHP - Leibniz Institute for High Performance Microelectronics – Frankfurt (Oder), Germany

TAICHIP Winter Schools are organized annually in winter at TAICHIP project partners’ premises. The events primarily target TalTech’s and partners’ PhD students and researchers, yet they are open to a wider research community. The programme covers topics related to technical and transferable skills for R&D&I of reliable and efficient AI-chip design and features a PhD Forum. The event facilitates establishing new collaboration opportunities within the TAICHIP network and with the international research community. The first edition is organized by IHP - Leibniz Institute for High Performance Microelectronics in Frankfurt-Oder, Germany. Its theme is “Reliable Hardware Infrastructure for Upcoming AI Chips”. 

General Chair:

• Fabian Vargas, IHP - Leibniz Institute for High Performance Microelectronics – Frankfurt (Oder), Germany

Programme Co-Chairs: 

• Marko Andjelkovic, IHP - Leibniz Institute for High Performance Microelectronics – Frankfurt (Oder), Germany
• Milos Krstic, IHP - Leibniz Institute for High Performance Microelectronics – Frankfurt (Oder), Germany

Programme

Monday, February 10, 2025

8:00 – 8:45 Registration

8:45 – 9:00 Opening Session and IHP’s Welcoming Address
Fabian Vargas, Marko Andjelkovic, Milos Krstic, IHP - Leibniz Institute for High Performance Microelectronics – Frankfurt (Oder), Germany

09:00 – 09:15 “Twinning Project TAICHIP: Towards Reliable and Efficient AI Chips”
Maksim Jenihhin, TalTech - Tallinn, Estonia

9:15 – 10:15 Keynote Talk “Challenges for Highly-Reliable High-Performance Processor Development”
Matthias Pflanz, IBM Research & Development - Boeblingen, Germany

10:15 – 10:30: Coffee-Break

10:45 – 15:15 PhD Forum (Poster presentations)

10:45 – 12:30 Short presentations (5-8-min, Power-Point):

• "Assessment and Enhancement of Hardware Reliability for Deep Neural Networks"
  Mohammad Hasan Ahmadilivani, TalTech - Tallinn, Estonia
• "Construction of Optimal Ternary All-Unidirectional Error-Detecting Codes" 
  Benjamin Glätzer, University of Potsdam – Potsdam, Germany
• "Extending the RISC-V ISA for SmartNIC Infrastructures"
  Kun Qin, Technical University of Munich – Munich, Germany
• "A Scalable Hardware Architecture for Efficient Sequential Learning at the Edge"
  Yicheng Zhang, Technical University of Munich – Munich, Germany
• "Detection and vulnerability assessment of microarchitectural side-channel attacks using Data Mining / Machine Learning"
  Muhammad Hassan, TalTech - Tallinn, Estonia
• "Translating Common Security Assertions Across Processor Designs: A RISC-V Case Study"
  Sharjeel Imtiaz, TalTech - Tallinn, Estonia
• "Secure Communication Protocols in Smart Grid Systems against cyber attacks"
  Abdul Haseeb, TalTech - Tallinn, Estonia
• "Design of Efficient Hardware Inference Engines for Edge AI"
  Ahsan Rafiq, TalTech - Tallinn, Estonia
• "Impact of Bias Temperature Stress, Irradiation and  Self-Heating Effects on Power VDMOS Transistor"
  Sandra Veljković, University of Niš – Niš, Serbia
• "Single Event Transient Robustness Analysis for Large Scale Circuits via Static Timing Analysis and Investigation of Optimisation Techniques"
  Christos Georgakidis, University of Thessaly – Thessaly, Greece
• "Analyzing Interconnect Effects on Transient Events via Static Timing Analysis"
  Nikos Chatzivangelis, University of Thessaly – Thessaly, Greece

12:30 – 13:30: Lunch

13:30 – 15:15 PhD Forum (Poster presentations and Discussions)

Session 1: (Part I) Architectures and AI-Based Applications

• 15:15 – 16:15 Lecture 1: “Approximate Fault-Tolerant Neural Network Systems”
  Alberto Bosio, EC-Lyon - Lyon, France

16:15 – 16:30 Coffee-Break

• 16:30 – 17:30 Lecture 2: “Asynchronous Interconnect Technology for Neuromorphic Computing”
  Davide Bertozzi, University of Manchester - Manchester, United Kingdom

Tuesday, February 11, 2025

Session 1: (Part II) Architectures and AI-Based Applications

• 09:00 – 10:00 Lecture 3: “PULP and AI Acceleration” 
  Frank K. Gurkaynak, ETHZ – Zürich, Switzerland

10:00 – 10:15: Coffee-Break

• 10:15 – 11:15 Lecture 4: “Hardware Design Challenges: Towards the integration of Deep Learning methods into next-generation Video Coding Algorithms” 
  Viktor Herrmann, University of Potsdam, Fraunhofer – Berlin, Germany

Session 2 (Part I): AI-Driven High-Performance Resilient Systems

• 11:15 – 12:15 Lecture 5: “AI-Driven Real-Time Reliability Prediction and Fault Mitigation in High-Reliability Chip Design for Space Applications”
  Junchao Chen, IHP - Leibniz Institute for High Performance Microelectronics – Frankfurt (Oder), Germany

12:15 – 13:15 Lunch

Session 2 (Part II): AI-Driven High-Performance Resilient Systems

• 13:15 – 14:15 Lecture 6: “Building RRAM-Powered AI Systems - Mitigating the von-Neumann Bottleneck”
  Markus Fritscher, IHP - Leibniz Institute for High Performance Microelectronics – Frankfurt (Oder), Germany
• 14:15 – 15:15 Lecture 7: “Fault-Tolerant CNN Accelerator with Reconfigurable Capabilities”
  Rizwan Tariq Syed, IHP - Leibniz Institute for High Performance Microelectronics – Frankfurt (Oder), Germany
• 15:15 – 16:15 Lecture 8: “Designing Robust DNN Systems for Safety-Critical Applications”
  Alessandro Veronesi, IHP - Leibniz Institute for High Performance Microelectronics – Frankfurt (Oder), Germany

16:30 - 18:00 TAICHIP Project Management Committee Meeting [participation is restricted to the MC members only]

19:00 – 21:00 Social Event: Dinner at Restaurant “Villa Casino”, Slubice, Poland (https://villa-casino.pl/de/)

Wednesday, February 12, 2025

Session 3: Processor AI-Based Fault-Injection Simulation

• 09:00 – 10:00 Lecture 9: “Using Machine Learning to accelerate Simulation-based Fault Injection”
  Li Lu, IHP - Leibniz Institute for High Performance Microelectronics – Frankfurt (Oder), Germany 
  

10:00 – 10:15 Coffee-Break

10:15 – 12:15 Visit to IHP’s Laboratories and Clean-Room

12:15 – 13:15 Lunch

Session 4: Social & Commercial Aspects: Ethics, Intellectual Property Patenting and Market Bring-up

• 13:15 – 14:15 Lecture 10: “Ethics and AI”
  Tobias Moebert, University of Potsdam – Berlin, Germany
• 14:15 – 15:15 Lecture 11: “IP Rights and Patent Writing”
  Thilo Henkel, Patent Attorney, Eisenführ Speiser Patentanwälte Rechtsanwälte PartGmbB – Berlin, Germany

15:15 – 15:30 Coffee-Break

• 15:30 – 16:30 Lecture 12: “Bringing Semiconductor Technology to Market: Cost, Benefit and Trade-off”
  Mirtha Valenzuela, Sarah Jann, IHP Solutions, IHP - Leibniz Institute for High Performance Microelectronics – Frankfurt (Oder), Germany 

16:30 – 16:45 Closing Session
Fabian Vargas, Marko Andjelkovic, Milos Krstic, IHP - Leibniz Institute for High Performance Microelectronics – Frankfurt (Oder), Germany

Venue

The 1st TAICHIP Winter School will take place at IHP Microelectronics, located at the following address:

IHP GmbH - Leibniz Institute for High Performance Microelectronics
Im Technologiepark 25
15236 Frankfurt (Oder)
Germany

Note: To reach IHP, participants should take a Tram (Line 4), the direction of “Markendorf Ort”, and exit at stop “Im Technologiepark”.

Main contact

• Dr. Fabian Vargas, This email address is being protected from spambots. You need JavaScript enabled to view it. 

Organizing Committee

• Dr. Fabian Vargas, This email address is being protected from spambots. You need JavaScript enabled to view it.
• Dr. Marko Andjelkovic, This email address is being protected from spambots. You need JavaScript enabled to view it.
• Dr. Milos Krstic, This email address is being protected from spambots. You need JavaScript enabled to view it. 

Secretary

• Dalia Hayek, This email address is being protected from spambots. You need JavaScript enabled to view it.
• Heike Wasgien, This email address is being protected from spambots. You need JavaScript enabled to view it.