Monday, 9 February 2026

Plenary day & keynotes (HG Audimax)

• Morning: Registration & welcome coffee; tutorials / lectures
• Afternoon: Keynote session (open, no registration required)
• Evening: Welcome Dinner (Dozentenfoyer)

Keynotes

• Domain-Specific Platforms: End-to-End Open Source Design from Dream to Reality, Luca Benini, ETH Zurich, Switzerland and Università di Bologna, Italy
• Brain-Inspired Principles for Scalable and Energy-Efficient Embedded Computing, Melika Payvand, University of Zurich and ETH Zurich, Switzerland
• Learning 3D Human Foundation Models, Siyu Tang, ETH Zurich, Switzerland
• Hardware Implementation Challenges for Post-Quantum Cryptography, Ingrid Verbauwhede, KU Leuven, Belgium
• Memory-Centric Computing: Solving Computing’s Memory Problem, Onur Mutlu, ETH Zurich, Switzerland

Tuesday-Thursday, 10-12 February, 2026

Parallel technical tracks 

• Daily registration / welcome coffee
• Hands-on sessions + technical talks
• Lunch at UniMensa
• Wednesday evening: Informal Apéro (ETZ J64)

Note: Exact room assignments and session timing are available in the PDF programme and on the ETH Zurich event page.

Track 1: End-to-End Open-Source Digital IC Design

Hands-on experience bringing an example design through a complete digital design flow using open-source EDA tools and an open 130nm PDK.

Topics

• Simulation with Verilator
• Synthesis using Yosys (incl. Yosys-Slang for SystemVerilog)
• Place & route using OpenROAD

Track structure

• 3 days (Tue–Thu), 9 modules (1.5h each)
• >50% hands-on exercises (computer lab)
• Daily technical talks by the PULP team

Capacity: 50 · Language: English · Prerequisites: Digital-circuits background; HDL knowledge a plus

Track 2: FPGA RISC-V Microcontrollers with Accelerators

Hands-on experience extending a RISC-V microcontroller to accelerate DSP (FIR filtering) using custom hardware, then deploying the extended SoC on an FPGA.

Topics

• RISC-V pipeline extensions with a custom instruction (FIR acceleration)
• Design and integration of a cooperative FIR hardware accelerator
• FPGA deployment on Zybo Z7; interaction through the debug unit

Capacity: 50 · Language: English · Prerequisites: Familiarity with SystemVerilog, C, and Make

Venue

ETH Zurich, D-ITET
Gloriastrasse 35, 8092 Zurich, Switzerland

Registration desk: ETZ building, ground floor (E floor). Public transport guidance and floor plans are included in the programme PDF.

Contacts

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