Publications

Scientific publications
Nr.
Codes
Authors
Title
Publication details
Links

1

(WP4/TUT)

M. Taheri, N. Cherezova, S. Nazari, A. Azarpeyvand, T. Ghasempouri, M.

Daneshtalab, J. Raik, M. Jenihhin

“AdAM: Adaptive Approximate Multiplier for Fault Tolerance in DNN Accelerators”

IEEE Transactions on Device and Materials Reliability, 25 (1), 66−75.

2

(WP4/TUT)

N. Cherezova, A. Jutman, M. Jenihhin

“FORTALESA: Fault-tolerant reconfigurable systolic array for DNN inference”

Microprocessors and Microsystems, 119, 105222.

3

(WP4/TUT)

D. Rahbari, M. Daneshtalab, M. Jenihhin

“An Efficient Architecture for Edge

AI Federated Learning with Homomorphic Encryption”

in IEEE Access, vol. 13, pp. 97919-97929, 2025

4

(WP4/TUT)

M. Taheri, P. Patne, N. Cherezova, A. Mahani, C. Herglotz and M. Jenihhin

“RL-Agent-based Early-Exit DNN Architecture Search Framework”

2025 IEEE 28th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS), Lyon, France, 2025, pp. 145-148.

5

(WP4/TUT)

S. Nazari, M. Taheri, A. Azarpeyvand, M. Afsharchi, C. Herglotz and M. Jenihhin

“Reliability-Aware Performance Optimization of DNN HW Accelerators Through Heterogeneous Quantization”

2025 IEEE 26th Latin American Test Symposium (LATS), San Andres Islas, Colombia, 2025, pp. 1-6.

6

(WP4/TUT)

A. Rafiq and M. Jenihhin

“XMULT: An Energy-Efficient Design of Approximate Multiplier”

2025 55th Annual IEEE/IFIP International Conference on Dependable Systems and Networks Workshops (DSN-W), Naples, Italy, 2025, pp. 111-114.

7

(WP4/TUT)

S. Nazari, M. Taheri, A. Azarpeyvand, M. Afsharchi, C. Herglotz and M. Jenihhin

“GENIE: GENetIc Algorithm-Based REliability Assessment Methodology for Deep Neural Networks”

2025 11th International Conference on Computing and Artificial Intelligence (ICCAI), Kyoto, Japan, 2025, pp. 264-271.

8

(WP4/TUT)

S. Nazari, M. Taheri, A. Azarpeyvand, M. Afsharchi, T. Ghasempouri, C. Herglotz, M. Daneshtalab, M. Jenihhin

“FORTUNE: A Negative Memory Overhead Hardware-Agnostic Fault TOleRance TechniqUe in DNNs”

2024 IEEE 33rd Asian Test Symposium (ATS), Ahmedabad, India, 2024, pp. 1-6.

9

(WP4/TUT/ECL)

A. Rafiq, A. Bosio, S. Pappalardo, M. Jenihhin

“AxEnMULT: Design of an Efficient and Reliable Approximate Encoding-Based Multiplier”

32025 IEEE Computer Society Annual Symposium on VLSI (ISVLSI). IEEE, 1−6.

10

(WP4/TUT)

H. Selg, K. Shibin, A. Tsertov, M. Jenihhin, P. Ellervee, J. Raik

“In-Field ML-Assisted Intermittent Fault Localization and Management in RISC-V SoCs”

37th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT’24)), October 8th - 10th, 2024, Harwell campus in Oxfordshire, UK.

[doi] [url] (open access)

11

(WP4/TUT)

P. Patne, M.Taheri, C. Herglotz, M. Jenihhin, M. Krstic and M. Hübner

“DART: Input-Difficulty-AwaRe Adaptive Threshold for Early-Exit DNNs”

IEEE

12

(WP4/TUT)

R. M. Kodamanchili, N. Cherezova, M. Taheri and M. Jenihhin

“Adaptive Fault Resilience for Early-Exit DNNsDART: Input-Difficulty-AwaRe Adaptive Threshold for Early-Exit DNNs”

IEEE Asian Test Symposium (ATS'25) (ATS-25), Tokyo, Japan.

13

(WP4/TUT)

M. H. Ahmadilivani, L. Aksoy, M. Eslami, J. Raik and A. Kuusik

“Cross-Layer Co-Optimized LSTM Accelerator for Real-Time Gait Analysis”

IEEE