TAICHIP "Chip Design" Industry Day 2026
October 9, 2026, Tallinn University of Technology, Estonia
Following the Industry Day held as part of the 1st TAICHIP Summer Workshop in 2025, the TAICHIP project organises a standalone Industry Day on Friday, October 9, 2026, at the Tallinn University of Technology. The day brings Estonian companies together with TAICHIP partners and invited speakers from the European chip design ecosystem. The programme covers what it takes to build a fabless semiconductor business, regional chip design competence centres, the state of open-source EDA and open PDKs, and MPW access from commercial to radiation-hardened technology nodes. The afternoon closes with a moderated discussion on the Estonian chip industry: where the real bottlenecks are, and which niches are worth pursuing.
The Industry Day is co-located with the IEEE Baltic Electronics Conference (BEC 2026), held in Tallinn on October 6-8, and is preceded by two invited talks by Dr. Yervant Zorian at TalTech on October 5 and 6. See co-located activities below. Participation is free of charge, but registration is required (deadline: September 28 October 1, 2026).
Online registration is closed. Please contact Kadri Mäger (
General Chair:
- Maksim Jenihhin, TalTech, Estonia
Programme Co-Chairs:
- Jaan Raik, TalTech / EIS, Estonia
- Artur Jutman, Testonica Lab / TalTech, Estonia
Programme
Friday, October 9, 2026 “Industry Day”
ICT-507 (5th floor), Akadeemia tee 15A, Tallinn
9:40 – 10:00 Welcome coffee
10:00 – 10:20 Welcome words and TAICHIP project overview
Maksim Jenihhin (TAICHIP project coordinator), TalTech, Tallinn, Estonia
10:20 – 11:00 So You Want to Start a Chip Company? Lessons from building, running and exiting a fabless semiconductor business
Michael Randt, founder of TRINAMIC Motion Control, Hamburg, Germany
Abstract and bio
11:00 – 11:40 Who Needs a Bavarian Chip-Design-Center?
Anton Klotz, Fraunhofer EMFT, Munich, Germany
Abstract and bio
11:40 – 12:00 Coffee Break
12:00 – 12:40 Open source chip design tools: status, opportunities and hurdles
Edmund Humenberger, Symbiotic EDA, Vienna, Austria
Abstract and bio
12:40 – 13:40 Lunch and Networking
13:40 – 14:20 IHP Open-PDK / Open-Tools, MPW and opportunities from commercial to radhard technology nodes
Fabian Vargas, IHP - Leibniz Institute for High Performance Microelectronics, Frankfurt (Oder), Germany
14:20 – 15:00 Building a chip and package from Estonia: solving a thermal challenge
Lauri Paal, Imaginal Microsystems, Estonia
Abstract and bio
15:00 – 15:20 Coffee Break
15:20 – 17:00 Estonian Chip Industry Discussion
Moderated by Artur Jutman, Testonica Lab / TalTech, and Jaan Raik, TalTech / EIS, Tallinn, Estonia
Opening talk: Overview of the Estonian chip design landscape in 2026, Andres Mellik, Metrosert Chip Competence Centre KIIP, Estonia
Discussion topics:
- Apart from the shortage of skilled personnel, what are the main showstoppers for Estonian companies that want to produce chips?
- Are there niche areas particularly suited to Estonian chip development, and if so, which ones?
17:00 – 17:10 Closing session
Maksim Jenihhin (TAICHIP project coordinator), TalTech, Tallinn, Estonia
19:00 – 21:30 Networking evening with drinks and snacks in Tallinn downtown (featuring discussions with Estonian companies and TAICHIP researchers)
Co-located activities, October 5-8
Several TAICHIP researchers are in Tallinn for the whole week, with technical meetings at TalTech from Sunday, October 4. The week opens with two invited talks by Dr. Yervant Zorian at TalTech, followed by an invited talk from ETH Zürich on Wednesday. The IEEE Baltic Electronics Conference runs from Tuesday, October 6 to Thursday, October 8 at the Nordic Hotel Forum in downtown Tallinn.
Monday, October 5, 2026
ICT-507AB (5th floor), Akadeemia tee 15A, Tallinn
11:00 – 12:00 Invited talk “Tracking the Microchip Journey in Armenia: Evolution & Horizons”
Yervant Zorian (President of Synopsys Armenia), Synopsys
Open to a broad audience, no chip design background needed. Hybrid event, on site and online.
Abstract and bio
Tuesday, October 6, 2026
ICT-507AB (5th floor), Akadeemia tee 15A, Tallinn
10:00 – 11:00 Invited talk “Lifecycle Health Management for Multi-Die Systems”
Yervant Zorian (Chief Architect and Fellow at Synopsys), Synopsys
Technical talk. Hybrid event, on site and online.
Abstract
Nordic Hotel Forum, Tallinn downtown
BEC 2026 opens. Conference programme and registration: taltech.ee/en/bec2026
Wednesday, October 7, 2026
ICT-507AB (5th floor), Akadeemia tee 15A, Tallinn
13:00 – 14:00 Invited talk “Designing reliable SoCs for physical AI in harsh environments”
Kai Berszin and Chen Wu, Integrated Systems Laboratory, ETH Zürich, Switzerland
Hybrid event, on site and online.
Abstract
Thursday, October 8, 2026
Nordic Hotel Forum, Tallinn downtown
11:00 – 12:30 TAICHIP Special Session at BEC 2026
- (5 min) Welcome and introduction to the TAICHIP project, M. Jenihhin
- (20 min) “Workload-Aware Online Self-Testing for Systolic Array Neural Network Accelerators”, G. Spera, A. Emmanuele, M. Barbareschi, A. Bosio Abstract
- (20 min) “Comparison of Ring Oscillators for On-Chip Monitoring of Supply Voltage and Temperature”, M. Andjelkovic, A. Duta, M. Marjanovic, M. Stamos, J. Nedeljkovic, T. R. Lenka, Z. Peric, M. Dincic, J. Nikolic, D. Dankovic, T. Nikolic, G. Nikolic, C. Sotiriou, M. Taheri, A. Jutman, M. Jenihhin, F. Vargas, M. Krstic Abstract
- (20 min) “Depth or Width? Soft-Error Resilience of Early-Exit DNNs”, R. M. Kodamanchili, N. Cherezova, M. Taheri, D. Bertozzi, M. Jenihhin Abstract
- (20 min) “PULP4Space: Developing Next-Generation Space Processing Platforms”, K. Berszin, C. Wu, A. Garofalo, F. K. Gürkaynak, L. Benini, ETH Zürich Abstract
12:30 – 13:00 Invited talk “Silicon lifecycle management in memory IPs: from on-chip aging sensors and processing telemetry datasets to failure prediction”
Fabian Vargas, IHP, Frankfurt (Oder), Germany
14:00 – 16:00 TAICHIP Advisory Board and Management Committee meeting
(Restricted to invited participants, room at the BEC venue)
19:00 TAICHIP dinner
Abstracts and speaker biographies
So You Want to Start a Chip Company?
Lessons from building, running and exiting a fabless semiconductor business
Michael Randt, founder of TRINAMIC Motion Control
Abstract. Starting a semiconductor company sounds intimidating: long development cycles, expensive mistakes, global supply chains and competitors that are often orders of magnitude larger. Yet the fabless model has made it possible for relatively small teams to build globally relevant semiconductor businesses.
This talk follows the journey from the initial idea to a sustainable company, and eventually to an exit. It discusses how to identify problems that justify custom silicon, turn technology into products customers actually want, survive the first development cycles, build a scalable organization and manage the realities of manufacturing, application support, sales and financing.
It also looks at what ultimately makes a semiconductor company strategically valuable to an acquirer, and why an exit should usually be the consequence of building a strong business rather than the original objective. Drawing on lessons from building TRINAMIC Motion Control, the talk is intended to encourage engineers to think beyond designing chips, toward creating semiconductor companies.
Bio. Michael Randt is an electrical engineer and founder of TRINAMIC Motion Control, a Hamburg-based fabless semiconductor company, now part of Analog Devices. He studied motor design and control engineering at the Technical University of Braunschweig. As founder and CEO, he led TRINAMIC from its beginnings as a semiconductor start-up through international growth and ultimately its acquisition by Maxim Integrated, which later became part of Analog Devices. Today he is active as an entrepreneur and investor, and supports initiatives aimed at strengthening the semiconductor and electronics ecosystem in Estonia.
Who Needs a Bavarian Chip-Design-Center?
Anton Klotz, Fraunhofer EMFT
Abstract. In 2023 the Bavarian Ministry of Economic Affairs, Regional Development and Energy decided to spend 50 million EUR on a Bavarian Chip-Design-Center. The project is executed by three Bavarian Fraunhofer institutes and five Bavarian universities. Its aim is to secure the competitiveness of the local economy in chip design and microelectronics. The project rests on three pillars: education, supply chain and ecosystem. Although focused on Bavaria, BCDC is strongly connected with German and European initiatives in chip design, and it also provides services to companies in Europe and worldwide.
Bio. Anton Klotz studied technical computer science in Germany. After 20 years at a large US EDA company, he now works as a business developer at Fraunhofer EMFT and supports the Bavarian Chip-Design-Center as sales manager. He is also industry chair at the DATE conference and is deeply involved in the European chip design community.
Open source chip design tools: status, opportunities and hurdles
Edmund Humenberger, Symbiotic EDA
Abstract. Open-source chip design has moved from a fragmented set of academic and community tools toward a more practical ecosystem for education, prototyping and early-stage semiconductor development. For decades, integrated circuit design depended on proprietary EDA tools and confidential Process Design Kits, which created high barriers for universities, small research groups, startups and emerging semiconductor communities.
The recent release of open Process Design Kits such as SkyWater SKY130A, GlobalFoundries gf180mcuD and IHP-SG13G2 has changed this landscape by enabling public access to manufacturable semiconductor technologies. In parallel, initiatives such as Efabless, ChipFoundry, Tiny Tapeout, IEEE PICO, UNIC-CASS, ChipPractice and the IEEE Open Silicon Initiative have connected open design infrastructure with training, mentoring, community participation and tape-out opportunities.
Open PDKs and individual tools are not sufficient on their own. Practical chip design requires reproducible toolchains, maintained environments, workflow integration, verification infrastructure and user support. This presentation traces the past, present and future of open-source chip design tools, from early community-driven EDA development to today's managed open-source design environments. It discusses how platforms such as BlueGarden aim to turn open tools into reliable, Docker-based and CI/CD-enabled engineering environments for education, research and professional design work. The talk demonstrates recent tape-out successes and argues that the future of open-source chip design depends not only on more open technologies, but also on sustainable infrastructure, institutional support, fabrication pathways and educational models that let students and engineers move from theory to real manufactured chips.
Bio. Edmund Humenberger is CEO of Symbiotic EDA, a Vienna-based company developing and supporting open-source EDA workflows. His work focuses on making hardware development more accessible through open FPGA tools, reproducible chip-design environments, CI/CD-based hardware flows and managed open-source toolchains. Since 2014 he has been closely involved in the open-source silicon ecosystem, including the broader adoption of open PDKs such as SkyWater SKY130, which helped make it possible to manufacture chips designed with open-source tools. Symbiotic EDA has supported customers and partners across industry, academia and research, including IHP, Qualcomm and Huawei, as well as open-source chip-design initiatives connected to Google.
Building a chip and package from Estonia: solving a thermal challenge
Lauri Paal, Imaginal Microsystems, Estonia
Abstract. Imaginal Microsystems is building a chip and its package around one requirement: extracting heat from the die at a useful temperature. The talk covers the engineering problem, where every layer between junction and coolant costs temperature, the direct-to-silicon alternative the company is developing, and what it has taken so far to run a fabless chip-and-package project from Estonia.
Bio. Lauri Paal leads product and commercial development at Imaginal Microsystems, an Estonian technology company developing chip technology and advanced packaging for liquid-cooled high-performance compute. He has more than 20 years of product and commercial leadership in international technology companies: running Eastern European operations at Tele2, building Skype's paid products globally from an early stage, and five years as Chief Product Officer at Kneip in Luxembourg, a fintech now part of Deutsche Börse Group.
Tracking the Microchip Journey in Armenia: Evolution & Horizons
Yervant Zorian, President of Synopsys Armenia, Chief Architect and Fellow at Synopsys
Invited talk, Monday, October 5, 11:00 to 12:00, ICT-507AB. Open to a broad audience, no chip design background needed.
Abstract. This presentation explores the transformation of Armenia's semiconductor landscape from a foundational Soviet computing hub into a competitive player in modern microchip design. It traces the nation's transition from early mainframe production to a specialized ecosystem dominated by global electronic design automation (EDA) leaders and advanced FPGA engineering. By analyzing the integration of multinational technology giants with local academic institutions, the session highlights how Armenia has cultivated a high-value engineering talent pool. Finally, it outlines future horizons for the sector, detailing plans to expand research and development hubs across Yerevan, Gyumri and Vanadzor, ultimately positioning the microchip industry as a vital catalyst for Armenia's sustainable, knowledge-driven economic growth.
Bio. Dr. Yervant Zorian is the President of Synopsys Armenia, Chief Architect and Fellow at Synopsys. Formerly he was Vice President and Chief Scientist of Virage Logic, Chief Technologist at LogicVision, and a Distinguished Member of Technical Staff at AT&T Bell Laboratories. He is currently President of the IEEE Test Technology Technical Council (TTTC), founder and chair of the IEEE 1500 Standardization Working Group, Editor-in-Chief Emeritus of IEEE Design and Test of Computers, and an Adjunct Professor at the University of British Columbia. He served on the Board of Governors of the Computer Society and CEDA, was Vice President of the IEEE Computer Society, and was General Chair of the 50th Design Automation Conference and the 50th International Test Conference, as well as several other symposia and workshops. Dr. Zorian holds more than 40 US patents, has authored four books, published over 350 refereed papers and received numerous best paper awards. A Fellow of the IEEE since 1999, he received the Industrial Pioneer Award in 2005 for his contribution to BIST, the IEEE Hans Karlsson Award for diplomacy in 2006, the IEEE Distinguished Services Award for leading the TTTC, the IEEE Meritorious Award for outstanding contributions to EDA, the Republic of Armenia's National Medal of Science in 2014, and the IEEE TTTC Lifetime Contribution Award in 2022. A member of the Central Board of the Armenian General Benevolent Union (AGBU), Dr. Zorian is the Founding President of the Armenian Virtual College, President of the AGBU Silicon Valley Branch, and Chairman of the ArmTech Congress Program Committee. He is a foreign member of the National Academy of Sciences of the Republic of Armenia and a member of the Board of Trustees of the American University of Armenia. He received an MS in Computer Engineering from the University of Southern California, a PhD in Electrical Engineering from McGill University, and an MBA from the Wharton School, University of Pennsylvania.
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Lifecycle Health Management for Multi-Die Systems
Yervant Zorian, President of Synopsys Armenia, Chief Architect and Fellow at Synopsys
Invited talk, Tuesday, October 6, 10:00 to 11:00, ICT-507AB. Technical talk.
Abstract. As traditional semiconductor innovation moves beyond transistor scaling in monolithic chips, multi-die architectures based on a wide range of chiplets are emerging as the foundation of next-generation intelligent systems. While these innovative solutions enable unprecedented levels of performance and scalability, they also introduce new challenges in test, quality, reliability, thermal and lifecycle management. This talk explores the design methodologies, DFT strategies and reliability frameworks required to ensure robust, high-quality chiplet and multi-die systems, highlighting the critical role of advanced self-test, repair and SLM technologies in enabling the future proliferation of such systems.
Bio. See the entry for Dr. Zorian's Monday talk above.
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Designing reliable SoCs for physical AI in harsh environments
Kai Berszin and Chen Wu, Integrated Systems Laboratory, ETH Zürich, Switzerland
Invited talk, Wednesday, October 7, 13:00 to 14:00, ICT-507AB
Abstract. Chen Wu and Kai Berszin present their current work on reliable SoC architectures. Chen covers her work on reliable networks-on-chip and gives an outlook on her future research direction. Kai gives a preview of his upcoming BEC talk and goes somewhat beyond its scope. The talk closes with a teaser of one of the current tapeouts in PULP, which targets physical AI in space.
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Workload-Aware Online Self-Testing for Systolic Array Neural Network Accelerators
Giovanni Spera, University of Naples Federico II, Italy; Antonio Emmanuele, University of Naples Federico II, Italy; Mario Barbareschi, University of Naples Federico II, Italy; Alberto Bosio, INL, Centrale Lyon, France
TAICHIP Special Session at BEC 2026, Thursday, October 8
Abstract. Deep Neural Networks (DNNs) are increasingly deployed in safety-critical systems, where real-time inference is commonly accelerated through dedicated architectures such as Systolic Arrays (SAs). In such accelerators, hardware faults may alter inference outcomes and lead to sample misclassifications, so regulations require self-testing mechanisms that can detect faults and identify their location to enable appropriate mitigation strategies. Exhaustive hardware testing solutions such as Built-In Self-Test typically require dedicated operating modes, resulting in service disruption and increased energy consumption. To address these limitations, this work proposes a test-pattern reduction strategy tailored to SAs. The approach retains only the test vectors covering the most impactful fault locations, first identifying them through fault injection and then selecting the patterns required to ensure their coverage. The approach was validated on LeNet-5 and ResNet-8 models mapped onto output-stationary SAs, showing test-pattern reductions of 63.2% and 64.4% respectively.
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Comparison of Ring Oscillators for On-Chip Monitoring of Supply Voltage and Temperature
Marko Andjelkovic, IHP, Frankfurt (Oder), Germany, and co-authors from IHP, the National Institute of Technology Silchar (India), the University of Niš (Serbia), the University of Thessaly (Greece), Tallinn University of Technology, Brandenburg University of Technology and the University of Potsdam
TAICHIP Special Session at BEC 2026, Thursday, October 8
Abstract. On-chip monitoring of supply voltage and temperature is crucial for runtime reliability management of complex systems such as artificial intelligence (AI) accelerators. Ring oscillators (ROs) are particularly suitable as on-chip sensors due to their simple fully digital design, small area, and low power consumption. The RO frequency is dependent on both supply voltage and temperature, but also on RO topology and number of delay stages. This paper presents a simulation-based comparison of five RO topologies with five delay stage counts (11, 21, 31, 41, and 51 stages). The simulation results for IHP's 130 nm process show that supply voltage variations cause significantly larger frequency changes than temperature variations over the investigated operating settings. The average absolute supply voltage and temperature sensitivities vary by approximately 25× and 9×, respectively, across the analyzed RO topologies. Based on sensitivities of individual ROs, possible RO pairs are identified for monitoring supply voltage, temperature, as well as both supply voltage and temperature.
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Depth or Width? Soft-Error Resilience of Early-Exit DNNs
Rama Mounika Kodamanchili, TalTech, Estonia; Natalia Cherezova, TalTech, Estonia; Mahdi Taheri, TalTech, Estonia and Humboldt University of Berlin, Germany; Davide Bertozzi, University of Manchester, United Kingdom; Maksim Jenihhin, TalTech, Estonia
TAICHIP Special Session at BEC 2026, Thursday, October 8
Abstract. While Dynamic Deep Neural Networks (D2NNs) have shown considerable potential for computational optimization, the impact of different architectural dimensions on their operational reliability remains underexplored. This study presents a comparative evaluation of two primary architectures, depth-wise and width-wise early-exit models, with respect to their fault resilience. Using Bayesian optimization, optimal early-exit configurations are generated for fault-free models, after which Fault Injection campaigns are run with bit-flips randomly injected in ResNet-18 and ResNet-50 models. Under fault-free conditions, the empirical evaluation shows that width-wise early-exit models achieve MAC reductions of up to 42.73× over static baselines, compared with 4.34× for depth-wise early-exit models. The width-wise early-exit models also show fault resilience at up to 6 Bit Error Ratio (BER) levels higher than their static counterparts, compared with up to 5 BER levels for depth-wise early-exit configurations. These results indicate that width-wise early-exit models provide a computationally efficient framework compared with depth-wise models, and are inherently more resilient to radiation-induced soft errors in edge deployments.
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PULP4Space: Developing Next-Generation Space Processing Platforms
Kai Berszin, Chen Wu, Angelo Garofalo, Frank K. Gürkaynak, Luca Benini, ETH Zürich, Switzerland
TAICHIP Special Session at BEC 2026, Thursday, October 8
Abstract. With the ever-increasing demand for higher-performance and energy-efficient on-board processing systems for space, research interest has risen toward assessing the space-readiness of high-performance and scalable processor architectures. Vector processors are a prominent example: by amortizing instruction fetch and decode over multiple computations, they alleviate the von Neumann bottleneck. While prior studies evaluated fixed SIMD paradigms on common spacecraft tasks, the flexibility offered by the RISC-V Vector Extension (RVV) has yet to be assessed on representative on-board workloads for the space domain. This work evaluates RVV on OBPMark, an openly available on-board processing benchmark suite released by the European Space Agency. All five OBPMark benchmarks were adapted to RVV and evaluated on an FPGA-prototyped ARA vector processor (4-lane, 4096-bit VLEN) against the scalar in-order CVA6 core. Results show that performance gains are strongly workload-dependent: two benchmarks yield no benefit, two show moderate speedups of 1.2× and 2.2×, and one highly data-parallel task achieves a 7.6× boost in performance. The analysis gives insight into the strengths and weaknesses of the ARA open-source vector processing engine and highlights directions for future developments.
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Venue
The TAICHIP Industry Day 2026 will take place at the Department of Computer Systems, Tallinn University of Technology.
Department of Computer Systems (5th floor)
Akadeemia tee 15A,
Tallinn 12618
Estonia
Main contact
Maksim Jenihhin
+372 620 2262 (Office)
ICT-529, Akadeemia tee 15A, Tallinn
Organizing Committee
- Maksim Jenihhin,
This email address is being protected from spambots. You need JavaScript enabled to view it. - Jaan Raik,
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Secretary
- Kadri Mäger,
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